FPGA-based Super Mario Bros
Hardware 2D graphics engine with real-time HDMI output and sprite pipeline rendering.
Overview
A fully hardware-synthesized implementation of Super Mario Bros running on an FPGA. The entire game logic, graphics pipeline, and display output are implemented in SystemVerilog — no CPU, no software, pure hardware logic.
Highlights
- Designed 11-stage pipelined sprite rendering architecture
- Implemented 720p60 HDMI pipeline with TMDS encoding
- Utilized ~16% FPGA BRAM for parallel sprite/palette memory
- Integrated collision detection and frame-synchronous game logic
Technical Details
The sprite pipeline processes multiple layers simultaneously, blending backgrounds, tiles, and sprites each frame. TMDS encoding drives a live HDMI signal at 720p60, with pixel data pulled from on-chip BRAM storing sprite sheets and palette maps.
Collision detection is fully synchronous with the rendering pipeline, ensuring the game state updates consistently frame-to-frame without drift.